ARINC 818 VIP

ARINC 818 VIP

STG’s ARINC 818 (ADVB) Verification IP is comprehensive protocol validation solution for ARINC 818 designs. It provides a complete BFM (Bus Functional Model) and a monitor with built-in checkers. It is designed for simple integration in testbenches and helps to reduce test time and accelerates verification processes.

Key Features and Benefits

  • Compliant to ARINC 818-2 specification
  • Supports serial bit ordering
  • Supports Full Video Frame format
  • Configurable link speed
  • 1.0625 Gbps
  • 1.5 Gbps
  • 1.62 Gbps
  • 2.125 Gbps
  • 2.5 Gbps
  • 3.1875 Gbps
  • 4.25 Gbps
  • 5.0 Gbps
  • 6.375 Gbps
  • 8.5 Gbps
  • 12.75 Gbps
  • Configurable Video frame rate per second
  • Supports 8B/10B encoding
  • Supports RGB pixel format
  • Supports “8-bit components, four components per transmission Word” packing format
  • Supports “Left to Right Top to Bottom” pixel array order
  • Supports 1:1 aspect ratio
  • Supports ancillary and video data transmission
  • Error detection and injection features
  • UVM compliant testbench
  • Supports widely known simulator tools (e.g QuestaSIM, VCS, Xcelium)
  • STG ARINC 818 VIP comes along with;
  • Detailed documentation showing how to integrate VIP
  • Example testbench suite
  • Pre-built sequences