ARINC 818-2 IP
STG’s ARINC 818 (ADVB) IP core is ARINC 818-2 compliant offering high-speed, low-latency video transmission. It can be used for both transmit and receive applications. This core supports configurable ADVBvideo formats and
uses a native interface to other video & image processing IP cores. IP core is compliant
of ARINC 818-2 and will be used for LADs, HUDs, MFDs, or HMDs. It has DO-254 DAL-A Compliant design and is used on Turkish Fighter-KAAN.
Key Features and Benefits
*IP Compliant to ARINC 818-2 specification
*Video TX and RX interface: Native interface
*Supports all aspect ratios and progressive/interlace videos
*Transmission medium – Optical and 75-ohm, 100-ohm, or 150-ohm Copper
*Customization as per customer’s Interface Control Document (ICD) can be provided such that custom data transmission & reception during the video blanking period can be applied
*Our IP core is not limiting the maximum resolution support and it completely depends on the FPGA transceiver speed i.e. transceiver is not included to the design
*DO-254 DAL-A Compliant design
*Receiver error and status reporting with support for user data
*Supports line-synchronous transmission
IP QUALITY MATRIX
This Data was Current On
Feb 01, 2024
Current IP Revision Number
R1.0
Date Current Revision was Released
Feb 01, 2024
Release Date of First Revision
Dec 01, 2023
Deliverables
Verification
IP Formats Available for Purchase
Source Code, Netlist
Is a Document Verification Plan Available?
Executable and documented plan
Source Code Formats
VHDL
Test Methodology
Directed Testing
High-Level Model Included?
N
Assertions
N
Integration Testbench Provided
Y
Coverage Metrics Collected
None
Integration Testbench Format
System Verilog
Timing Verification Performed
Y
Code Coverage Report Provided
Y
Timing Verification Report Available?
Y
Functional Coverage Report Provided?
Y
Simulators Supported
Synopsys VCS
UCFs Provided?
UCF
Commercial Evaluation Board Available?
Y
Hardware Validation
FPGA Used on Board
Kintex7
Validated on FPGA
Y
Software Drivers Provided?
N
Hardware Validation Platform Used
AV7K325,ZC705
Driver OS Support
N/A
Industry Standard Compliance Testing Passed
N/A
Code Optimized for any FPGA vendor?
Y, Xilinx
Are Test Results Available?
Y
Standard FPGA Optimization Techniquies
Interface
Custom FPGA Optimization Techniquies
None
Synthesis Software Tools Supported/Version
Xilinx Vivado/No version Limit
Static Timing Analysis Performed
Y
AXI Interface
N/A, Native